1. Field of the Invention
The present invention relates to an apparatus for testing the electrostatic breakdown of a semiconductor device and for thereby securely and stably monitoring the electrostatic breakdown using a charged device model which has been damaged due to electrostatic charges stored on a dielectric package of the semiconductor device.
2. Description of the Prior Art
An MOS IC, as being highly integrated and made minute, is likely to experience an electrostatic breakdown since it has been made fine at present, e.g., less than 2 .mu.m in its designed pattern as well as less than 35 .mu.m in its gate oxide film. In addition, such an electrostatic breakdown may also originate from diversified packagings thereof.
A flat package, for example, tends to have a higher electrostatic capacity due to the mold resin thereof being made thinner, and hence to have more electric charges stored thereon. Moreover, a chip-on board IC allows the chip to be charged with electrostatic charges directly thereon. The electrostatic charges may damage a gate oxide film and a junction thereof.
The mechanism of this electrostatic breakdown phenomenon can be caused by allowing the package surface to be charged with static electricity, which is then discharged through a lead.
The present applicant has proposed "the charged package method", as a method of testing the electrostatic breakdown of a semiconductor device by charging a package thereof with electricity, which has been described in detail in Japanese Laid-Open Patent Publication No. 60-73375. By the use of this charged package breakdown testing method, it has been possible to determine the equivalent parameters of an electrostatic breakdown phenomenon caused due to charges stored on a package, and the design of the circuit, the shape of the package, and the like.
It is necessary to effect the steps of charging an IC to be tested with electricity and of discharging it from leads of the IC in repetition for each lead and for each voltage due to the charges on the package. For example, in testing an IC with 64 pins, 64.times.several times or several tens of times repetitions are needed.
Furthermore, it takes several seconds to lower a voltage of a power source to zero, owing to the internal capacitance of the power source. Thus, after the test with one lead, it is impossible to start the test with another lead instantly.